A common requirement for semiconductor processing and the resulting devices produced by the processes is an interlevel dielectric (“ILD”) or intermetal dielectric “(IMD”). These layers are disposed between vertically stacked layers containing metal conductors. In current advanced semiconductor processes, the conductors are formed in damascene processes. During processing, an IMD layer is formed in a deposition stage. Anisotropic etching is used to define trenches or vias in the IMD. Metal is formed within the trenches and vias using damascene processes. A particular metal layer is completed by a chemical mechanical polish (“CMP”) process to remove the excess conductor material and form conductors contained in trenches within the IMD. Subsequent IMD layers are formed and complex interconnections and wiring using multiple levels of metallization may be completed by repeating these steps.
Wet processing is used to complete the IMD layers. If the IMD layer is not of sufficient mechanical strength, damage may occur to the IMD layer in the wet processes such as wet cleans following etch. Recent advances in materials include forming low-k IMD layers using porogens by vapor deposition. After the deposition is complete, the porogens are removed with a cure process. The IMD layers are patterned into, for example, trenches, by etching. Wet processing is used to complete the IMD layers. If the IMD layer is not of sufficient mechanical strength, damage may occur to the IMD layer in the wet processes such as wet cleans following etch. While it is known that a longer cure of the IMD material can be beneficial in increased mechanical strength of the dielectric layers, increasing cure time also increases moisture absorption and creates lower throughput, increasing cost and reducing wafer yield per hour. Increased moisture absorption can result in blurred lines and distorted lines or loss of lines in the wet processes.
A continuing need thus exists for methods and apparatus for advanced low-k dielectric layers with high mechanical strength without the disadvantages currently experienced using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.